The present invention generally relates to the design and fabrication of systems-on-chip (SoC) and to methods and arrangements associated with the same.
Generally, systems-on-chip (SoC) are increasingly relying on reuse of pre-designed and pre-verified intellectual property (IP) blocks. However, in order to build a system-on-chip the designer has to manually instantiate these IP blocks and create all the necessary interconnections between them. This is a time-consuming and error-prone process
More particularly, with the continuing increases in silicon density and associated rise in design complexity, more design projects are relying on methods of core reuse to complete their very large scale integration (VLSI) chips within alotted time frames. These ever-increasing silicon densities have now made it affordable to integrate the majority of the system on a single VLSI device.
The integration of the central processor unit (CPU), memory and peripherals within a single VLSI device adds system complexities to what used to be a standard application-specific intergrated circuit (ASIC) development. The typical ASIC designer developing a SoC often does not have resources available to deal with the inherent system complexities as wells as the complexities of the cores themselves, and to maintain the schedule of a standard ASIC development.
The use of pre-designed and pre-verified IP blocks (henceforth referred to as cores) has helped reduce expenditures of time and cost related to large SoCs. However, the lack of appropriate tools and the increasing complexity of such cores make them inherently difficult to use. The process of integrating several cores in an SoC is currently a manual and error-prone process which requires the designer to understand the details of the cores and how they should be interconnected. Currently, SoC integration involves the use of pre-designed cores in a very low-level manner, that is, cores are used in the same way as other low- level components, even though they usually represent much larger functions. Currently, there is no high- level abstraction that allows cores to be used easily and without the need for an expert designer.
In A. Rincon, W. Lee and M. Slatery, xe2x80x9cThe Changing Landscape of System-on-a-Chip Designxe2x80x9d (IBM MicroNews, 3rd Quarter 1999, Vol.5, No.3, IBM Microelectronics) and A. Rincon, C. Cherichetti, J. Monzel, D. Stauffer and M. Trick, xe2x80x9cCore Design and System-on-a-Chip Integrationxe2x80x9d (IEEE Design and Test of Computers, October/December 1997), complex system-on-chip examples are discussed which illustrate the high complexity of current cores and the difficulties in integrating them into a single VLSI chip.
In traditional ASIC design flows, there is a high-level of abstraction represented by the register-transfer level (RTL) language description, using hardware description languages such as VHDL or Verilog. In this context, the design is written at a high-level and it is mapped to a low-level (gate-level netlist) by logic synthesis tools. In current SoC design flows, there is no similar high-level of abstraction. SoC designs are described directly at the core level (similar to gate-level) by manually instantiating the cores and the interconnections among their pins. In other words, core-based SoC design today is at a similar stage that ASIC design was prior to the widespread use of hardware description languages and logic synthesis tools.
Essentially, the only high-level description of an SoC in the context of conventional arrangements is the initial design document which is text-based and used for documentation purposes only, and thus is not synthesizable. Since there are apparently no higher-levels of abstraction for core-based SoC design that are automatically synthesizable, the capabilty of reusing pre-designed IP blocks is severely limited, thus constituting a major drawback to reducing expenditures of time and cost in connection with SoC designs.
In view of the foregoing, a need has been recognized in connection with providing high-level abstraction that allows a system-on-chip to be designed at a very high-level and automatically synthesized down to real cores and interconnections.
In accordance with at least one presently preferred embodiment of the present invention, a methodology and algorithms for SoC design are contemplated in which cores are used based on the concept of a synthesizable xe2x80x9cvirtual designxe2x80x9d. As a result, the level of abstraction and productivity for SoC integration is raised by enabling the designer to work at the virtual component level.
Preferably, the SoC is designed at the virtual level as a grouping of virtual components. Various methods and algorithms contemplated herein thence automatically synthesize a xe2x80x9creal designxe2x80x9d from the initial virtual design. (The term xe2x80x9creal designxe2x80x9d, as employed herein, refers to the complete and final top-level netlist of the SoC with all the necessary cores and interconnections.) Two broad aspects are particularly contemplated herein, namely, a xe2x80x9cvirtual designxe2x80x9d and a xe2x80x9cvirtual-to-real synthesis enginexe2x80x9d.
In one aspect, the present invention provides a method of predetermining interconnections between at least two cores in a system-on-chip, the method comprising: establishing a virtual design for the system-on-chip, the virtual design including at least two virtual components, at least one virtual pin associated with each virtual component, and at least one virtual interconnection between at least one pair of virtual pins; and automatically transforming the virtual design into a real design, the real design including at least two real components, at least one real pin associated with each real component and at least one real interconnection between at least one pair of real pins; wherein the transforming step comprises determining the at least one real interconnection based on the compatibility between different real pins.
In another aspect, the present invention provides a system for predetermining interconnections between at least two cores in a system-on-chip, the system comprising: a virtual design system which establishes a virtual design for the system-on-chip, the virtual design including at least two virtual components, at least one virtual pin associated with each virtual component, and at least one virtual interconnection between at least one pair of virtual pins; and a transforming system which automatically transforms the virtual design into a real design, the real design including at least two real components, at least one real pin associated with each real component and at least one real interconnection between at least one pair of real pins; wherein the transforming system is adapted to determine the at least one real interconnection based on the compatibility between different real pins.
Furthermore, the present invention provides a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for predetermining interconnections between at least two cores in a system-on-chip, the method comprising the steps of: establishing a virtual design for the system-on-chip, the virtual design including at least two virtual components, at least one virtual pin associated with each virtual component, and at least one virtual interconnection between at least one pair of virtual pins; and automatically transforming the virtual design into a real design, the real design including at least two real components, at least one real pin associated with each real component and at least one real interconnection between at least one pair of real pins; wherein the transforming step comprises determining the at least one real interconnection based on the compatibility between different real pins.
For a better understanding of the present invention, together with other and further features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, and the scope of the invention will be pointed out in the appended claims.